25. October 2017 - 9:00
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Arm Cortex processor behaviors Community | | Wednesday, 25. October 2017


Introductory knowledge of either the A, R, or M profile of the Arm architecture.

The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers.
Delivery Method:



1 hour



Topic overview

Simple Sequential Model

Instruction fetching optimizations 

Intro to instruction fetching optimizations

Branch prediction overview

Branch prediction method (return stack)

Branch prediction method (conditional branch prediction)

Effects of branch prediction

Data processing optimizations 

Data processing optimizations - overview
Multiple execution pipelines
Speculative execution
Register dependencies
Cortex-A, R, and M interrupt behaviors

Data memory access optimizations

Data memory access optimizations - overview

Caching (cache eviction)

Caching (cache pre-fetching performance

Caching (cache maintenance - multi-caching)


Re-ordering overview

Re-ordering commands

ISB and DSB example

Barriers and speculative access


Cortex-A summary

Cortex-R summary

Cortex-M summary

Language: This course is presented in English.
Delivery Method: Bitesized video content
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You will have 3 months access to this community.